1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a self-aligned contact method of forming a contact for a source/drain region of the semiconductor device.
A claim of priority is made to Korean Patent Application No. 2002-73049, filed on 22 Nov. 2002, which is incorporated herein in its entirety by reference.
2. Description of the Related Art
As semiconductor devices become highly integrated, the distance between device components decreases, making it difficult to employ conventional patterning techniques. For example, when a contact is formed in an active region of a dynamic random access memory (DRAM) device, a contact area is so small that many problems are encountered during patterning of layers of the device. As such, a technique known as self-aligned contact formation has been introduced in an effort to combat the problems associated with the patterning of extremely small dimensions.
FIGS. 1 and 2 are cross-sectional diagrams for explaining a conventional self-aligned contact formation process. Referring first to FIG. 1, an isolation insulating film 1110 is formed in a semiconductor substrate 100 to define a device formation region. A gate 1120 is formed on the semiconductor substrate 100. The gate 1120 includes a gate dielectric film (not shown), a gate conductive film 1123 and 1125, a mask insulating film 1127 and sidewall spacers 1129. A source region 1105a and a drain region 1105b are formed at respective sides of the gate 1120. An etch stop 1140 is formed on the resultant structure of the semiconductor substrate 100, a first interlayer insulating film 1150 is formed on the etch stop 1140, and a self-aligned contact hole 1160a is formed in the first interlayer insulating film 1150 through a predetermined patterning process.
Referring to FIG. 2, the etch stop 1140 remaining in the self-aligned contact hole 1160a is removed by dry etching, thereby exposing the source region 1105a and the drain region 1105b. The contact hole 1160a is filled with conductive polysilicon (not shown) to form a contact pad.
In the conventional self-aligned contact formation process, over etching of the etch stop 1140 remaining in the contact hole 1160a is needed to sufficiently expose the underlying surface of the silicon substrate 100. Unfortunately, due to characteristics of dry etching, the over etching can damage the silicon substrate 100, which in turn can increase the contact resistance of the contact hole 1160a. The result can be contact failures and increased leakage current.